1. Field of the Invention
The present invention is directed to integrated circuit fabrication and test methodologies, and, particularly, to a novel method and system for in-line monitoring of hysteresis effects exhibited by silicon-on-insulator (SOI) wafer manufacturing process.
2. Discussion of the Prior Art
It is commonly known that the SOI floating body results in hysterises effects whereby the delay through a set of SOI circuits depends on the input history. Manufacturing control of this history effect is critical. Methods to measure SOI hysteresis effects are readily available, but require the use of high speed measurement equipment and high-frequency test probes that are not amenable to inline manufacturing high-throughput and inexpensive testing/monitoring/characterization.
It would be highly desirable to provide an SOI hysteresis test structure that eliminates the need for non-standard, high-frequency inline test equipment and test probes.
Moreover, it would additionally be highly desirable to provide an SOI hysteresis test structure that may be wholly implemented within the kerf of the chip, separate from other active chip circuits.